www.kersemi.com 1 power mosfet irfr9310, IRFU9310, sihfr9310, sihfu9310 features ? p-channel ? surface mount (irfr9310/sihfr9310) ? straight lead (IRFU9310/sihfu9310) ? advanced process technology ? fast switching ? fully avalanche rated ? lead (pb)-free available description third generation power mosf ets from vishay utilize advanced processing techniques to achieve low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the dpak is designed for su rface mounting using vapor phase, infrared, or wave soldering techniques. the straight lead version (irfu/sihfu series) is for through-hole mounting applications. power dissipation levels up to 1.5 w are possible in typical surface mount applications. note a. see device orientation. product summary v ds (v) - 400 r ds(on) ( )v gs = - 10 v 7.0 q g (max.) (nc) 13 q gs (nc) 3.2 q gd (nc) 5.0 configuration single s g d p-channel mosfet d pak (to-252) ipak (to-251) a v aila b le rohs* compliant ordering information package dpak (to-252) dpak (to-252) dpak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free irfr9310pbf irfr9310trlpbf a irfr9310trpbf a irfr9310trrpbf a IRFU9310pbf sihfr9310-e3 sihfr9310tl-e3 a sihfr9310t-e3 a sihfr9310tr-e3 a sihfu9310-e3 snpb irfr9310 irfr9310trl a irfr9310tr a - IRFU9310 sihfr9310 sihfr9310tl a sihfr9310t a - sihfu9310 absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds - 400 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 1.8 a t c = 100 c - 1.1 pulsed drain current a i dm - 7.2 linear derating factor 0.40 w/c single pulse avalanche energy b e as 92 mj repetitive avalanche current a i ar - 1.8 a repetitive avalanche energy a e ar 5.0 mj maximum power dissipation t c = 25 c p d 50 w peak diode recovery dv/dt c dv/dt - 24 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d
www.kersemi.com 2 irfr9310, IRFU9310, sihfr9310, sihfu9310 note a. when mounted on 1" square pcb (fr-4 or g-10 material). thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --50 maximum junction-to-case (drain) r thjc --2.5 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 400 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = - 1 ma - - 0.41 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 400 v, v gs = 0 v - - - 100 a v ds = - 320 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 1.1 a b --7.0 forward transconductance g fs v ds = - 50 v, i d = - 1.1 a 0.91 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 270 - pf output capacitance c oss -50- reverse transfer capacitance c rss -8.0- total gate charge q g v gs = - 10 v i d = - 1.1 a, v ds = - 320 v, see fig. 6 and 13 b --13 nc gate-source charge q gs --3.2 gate-drain charge q gd --5.0 turn-on delay time t d(on) v dd = - 200 v, i d = - 1.1 a, r g = 21 , r d = 180 , see fig. 10 b -11- ns rise time t r -10- turn-off delay time t d(off) -25- fall time t f -24- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 1.9 a pulsed diode forward current a i sm --- 7.6 body diode voltage v sd t j = 25 c, i s = - 1.1 a, v gs = 0 v b --- 4.0v body diode reverse recovery time t rr t j = 25 c, i f = -1.1 a, di/dt = 100 a/s b - 170 260 ns body diode reverse recovery charge q rr - 640 960 nc forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) d s g s d g
www.kersemi.com 3 irfr9310, IRFU9310, sihfr9310, sihfu9310 typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.1 1 10 1 10 100 20s pulse width t = 25 c j top bottom vgs -15v -10v -8.0v -7.0v -6.0v -5.5v -5.0v -4.5v -v , drain-to-source voltage (v) -i , drain-to-source current (a) ds d -4.5v 0.1 1 10 1 10 100 20s pulse width t = 150 c j top bottom vgs -15v -10v -8.0v -7.0v -6.0v -5.5v -5.0v -4.5v -v , drain-to-source voltage (v) -i , drain-to-source current (a) ds d -4.5v 0.1 1 10 4 5 6 7 8 9 10 v = -50v 20s pulse width ds -v , gate-to-source voltage (v) -i , drain-to-source current (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d -10v -1.8a
www.kersemi.com 4 irfr9310, IRFU9310, sihfr9310, sihfu9310 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 1 10 100 0 100 200 300 400 500 -v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss gs gd , ds rss gd oss ds gd c iss c oss c rss 0 4 8 12 16 0 4 8 12 16 20 q , total gate charge (nc) -v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 -1.1a v = -80v ds v = -200v ds v = -320v ds 0.1 1 10 1.0 2.0 3.0 4.0 5.0 -v ,source-to-drain voltage (v) -i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0.1 1 10 100 10 100 1000 operation in this area limited by r ds(on) single pulse t t = 150 c = 25 c j c -v , drain-to-source voltage (v) -i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
www.kersemi.com 5 irfr9310, IRFU9310, sihfr9310, sihfu9310 fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 25 50 75 100 125 150 0.0 0.4 0.8 1.2 1.6 2.0 t , case temperature ( c) -i , drain current (a) c d p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
www.kersemi.com 6 irfr9310, IRFU9310, sihfr9310, sihfu9310 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit a r g i as 0.01 t p d.u.t. l v ds + - v dd - 20 v dri v er 15 v i as v ds t p 25 50 75 100 125 150 0 50 100 150 200 250 300 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom -0.49a -0.7a -1.1a q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
www.kersemi.com 7 irfr9310, IRFU9310, sihfr9310, sihfu9310 fig. 14 - for p-channel p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = - 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - - - - + + + * v gs = - 5 v for logic le v el and - 3 v dri v e de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g compliment n -channel of d.u.t. for dri v er
|
